1. Field of the Invention
The present invention relates to semiconductor packages and methods of manufacturing the same, and, more particularly, to a wire-bonding-type semiconductor package and a method of manufacturing the same.
2. Description of Related Art
With the development of electronic industry, electronic products at the market have demands for light weight, compact size, high performance and multi functions. The achievement of an ideally light, compact and fast electronic product depends on developments of high memory capacity, high operation frequency and low voltage requirement of IC components. However, the high memory capacity, high operation frequency and low voltage requirement of IC components continuously improve upon the density of electronic circuits and elements on an IC component and the density of I/O connectors providing transmission for electronic circuit signals and power.
In order to contain more electronic components, such as capacitors, resistors, inductors, RF passive devices and other passive components to satisfy the needs of the industry, BGA semiconductor device is thus developed.
However, some semiconductor devices, such as communication or RF semiconductor devices, usually need to electrically connect a plurality of passive components such as resistors, inductors, capacitors and RF passive devices to a packaged semiconductor chip, and thus the semiconductor chip has a specified current characteristic. A BGA semiconductor device, for example, although has a plurality of passive components arranged on the substrate surface, in order to prevent those passive components from blocking electrical connections and arrangements between the semiconductor chip and a plurality of conductive lands. Traditionally, those passive devices are arranged at corner positions of a substrate or layout areas of a substrate in addition to mounting regions of semiconductor chips.
Nevertheless, the limited arranging positions of passive devices will reduce the routability of a circuit layout, and positions of conductive lands further result in a limited arrangement numbers of those passive devices, which is disadvantageous for the development trends of a high integration of a semiconductor device. Additionally, the arrangement numbers of passive devices dramatically increase in response to a demand for high performance of a semiconductor package. In the prior art, the substrate surface has to contain a plurality of semiconductor chips and more passive devices, which may cause an increase of package substrate areas, and force an increase of a package volume, and does not accord to the development trends of a compact semiconductor package.
Please referring to FIG. 1, based on above problems, a conventional semiconductor package 1 has a plurality of passive devices arranged on a region between a semiconductor chip 13 and conductive lands 100. However, with the increased numbers of I/O connectors on a unit area in a semiconductor device, the numbers of bonding wires 14 also increase and generally the height of a passive device 11 (0.8 mm) is higher than a semiconductor chip 13 (0.55 mm). In order to prevent a bonding wire 14 from contacting a passive device 11 causing a short circuit, the bonding wire 14 have to be pulled up and cross over the passive device 11, which increase the bonding difficulty and the length of a wire loop. Further, since the weight of the bonding wire 14 itself, the pulled up bonding wire 14 may sag and contact to the passive device 11 causing a short circuit if there is no support for the bonding wire 14. Moreover, the bonding wire 14 is made by gold and aluminum materials, this method not only increase the complexity of a manufacture process, but the increased length of a bonding wire 14 wire loop also significantly raise the cost of the bonding wire 14.
Therefore, how to prevent above problems of the prior art is substantially an issue desirably to be solved in the industry.